What does EUV lithography have in common with samurai swords? Read about some of the highlights of 20 years of EUV lithography innovation at ASML, recognized by a special award from the European Patent Office.
A chemical compound of argon and fluorine. An ArF laser uses argon and fluorine gases to produce light with a wavelength of 193 nm. This technology is the light source that is being used in today's most advanced immersion systems capable of imaging 38 nm features. In recent years, wavelengths of light used to image circuits on chips have shortened from 365 nm (older generation = I-line) to 248 nm (KrF technology) to 193 nm (new generation = ArF technology).
Our systems backlog and net bookings include all system sales orders for which written authorizations have been accepted (for EUV starting with the NXE:3350B).
ASML reveals its backlog once per quarter during its financial results announcements.
The book-to-bill ratio is a measure of the total orders taken or ‘booked’ over the total orders for which those same companies have received payment or ‘billed.’ For example, a book-to-bill ratio of 0.9 means that for every dollar of orders billed; only US$ 0.90 of the orders were booked.
The book-to-bill ratio is important when looking at the chipmakers – ASML’s clients -- because it gives an overall sense of supply and demand. When the number is below 1.00, it suggests that there is more supply than demand. Chipmakers typically buy new equipment when demand is high and supply is low.
Chips are semiconductor integrated circuits, commonly made from silicon. The process of making chips typically consists of building up many layers and repeating many processing steps – including lithography – during which hundreds of copies of an integrated circuit are formed on a single wafer.
Integrated circuits or chips are made in a clean room – an area virtually free of dust and other airborne particles. The air in the clean room is circulated through filters that capture any particles larger than the filter’s pore size.
If particles were to land on a wafer during processing, the chips created from that wafer would have defective structures and would not function.
Semiconducting, insulating and conducting layers are deposited and selectively etched on a chip to build three dimensional devices, circuits and connectors. Each layer is deposited by one of several processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Molecular Beam Epitaxy (MBE) and Atomic Layer Deposition (ALD).
A die is an unpackaged chip – a piece of the wafer after the semiconductor fabrication process is complete and the wafer has been sliced. Typically, silicon wafers are sliced into hundreds of rectangular die. A die will have about 40 layers, patterned and shaped using lithography into electronic circuits during fabrication, which are built on top of the wafer. From bare to finished wafer, every die on the wafer will have passed the lithography tool at least one time for each layer.
Insulating material on a chip that separates metal layers from one another.
A circuit pattern on a mask (reticle) is projected onto photoresist-covered wafer using UV light. The light reacts with the resist and transfers the circuit image into the resist; afterwards the image is transferred to the wafer. This area of the wafer will eventually become part of an integrated circuit. The wafer is then moved (stepped) and the process is repeated, until the wafer is covered with many identical patterns, all of which will become ICs.
Extreme UltraViolet (EUV) technology is the most credible technology for the industry to continue to print smaller features onto ever-more complex chips. EUV lithography is done in a vacuum using a plasma to produce EUV light using highly sophisticated mirrors instead of lenses to project the circuit patterns onto silicon wafers. Today’s silicon chips have features as small as 40 nanometers – less than a few hundred atoms across. EUV lithography tools will be used to print features 22 nm and smaller. Using EUV to print transistors this small is equivalent to printing an image the size of a human eye on the surface of the earth from a space shuttle . . . and then printing another image on top of the first one with perfect alignment.
A 'fab' is an integrated circuit 'fabrication' facility, i.e. a chip manufacturing plant. A fabless company is one that outsources the production of its chip designs.
Total range of focus that can be 'tolerated'; that is, the usable range of focus that keeps a printed feature within several target specifications, such as line width and overlay. Depth of focus decreases with shorter wavelength light and larger Numerical Apertures.
A catadioptric lens design combines glass lens elements with mirrors to create a hyper NA lens. The TWINSCAN™ XT:1700Fi was the first ASML tool to contain such a lens.
Field size is the area on a wafer that is imaged in a single exposure. The maximum field on a wafer is typically 26 mm by 33 mm. There are roughly 125 fields on an average wafer. One field can image several ICs.
The size of the smallest feature fabricated on any Integrated Circuit (IC). Shrinking the critical dimension enables semiconductor manufacturers to make a given IC design smaller, reducing the cost of the IC, or to include more transistors in the IC to increase its functionality.
An excimer laser is a high-powered light source used to produce narrow bandwidth light in the Deep Ultraviolet spectrum; different wavelengths are possible by using different combinations of gases. Excimer lasers using a mixture of Krypton and Fluorine gases are used to produce light at 248 nm wavelength while lasers using Argon and Fluorine are used to produce light at 193 nm.
A state-of-the-art method for making smaller chips by splitting complex patterns into two (or more) simpler/less dense ones. There are several double patterning techniques; all are used in combination with lithography and involve extra processing steps (masks, lithography, etching, etc.). However, double patterning enables Moore's law to continue, bridging the gap to high-volume EUV technology. When EUV enters mass production, single patterning/exposure lithography will again be used to further shrink chip features.
Advanced nanotechnology R&D center at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, State University of New York (SUNY).
Improvement of the entire chip-imaging process by optimizing wafer lithography, computational lithography and layout, for better system performance and value of ownership.
CDU (CD Uniformity)
A measure of the pattern fidelity (variation in feature size) printed on a wafer.
DDL (Double Dipole Lithography)
ASML's patented Double Dipole Lithography is a technique that allows chipmakers to create smaller chip features by splitting dense circuit patterns into horizontal and vertical masks, then exposing them sequentially. DDL uses horizontally polarized light in one exposure, followed by vertically polarized light in another. DDL lowers IC production costs and reduces cycle time by allowing the use of one less etch step than most other double-patterning approaches.
A branch of lithography using algorithms to enhance the design and manufacture of semiconductor chips. Key areas include litho-aware design, fast OPC, OPC verification, Double Dipole Lithography (DDL) and SMO.
A semiconductor material comprising two or more chemical elements such as Gallium Arsenide (GaAs). Compound semiconductors are more difficult to process than silicon so chips are generally fabricated on smaller wafers.
Dynamic Random Access Memory, a type of volatile memory used in most personal computers.
I-line refers to a line in the emission spectrum of mercury (a mercury-lamp source producing light with a wavelength of 365 nm is used in certain types of scanner). I-line scanner technology is well established but is now used in systems that offer high value-of-ownership and productivity for specific chip layers. In recent years, wavelengths of light used to fabricate the most detailed layers on chips have shortened from 365 nm (i-line technology) to 248 nm (KrF technology) to 193 nm (ArF technology) down to 13.5 nm for future systems (EUV technology).
Immersion lithography uses a liquid between the wafer and the lens to increase the depth-of-focus and resolution of the projected image (by increasing the numerical aperture (NA) of the lens). The primary advantage of immersion lithography is that it enables 193 nm wavelength scanners to image 38 nm features (and possibly below) in a single exposure.
ICs or integrated circuits
Integrated circuits (ICs) or 'chips' are tiny interconnected electronic components (circuits) contained on a thin slice of semiconductor material. Today's most advanced chips contain billions of components. The process of making chips involves many steps – including numerous lithography stages – during which hundreds of copies of the chip are printed onto a single wafer.
The krypton fluoride laser is a member of the excimer laser family and produces high-energy light pulses at a wavelength of 248 nm. KrF technology is used in scanners producing layers with features from 0.25 micron to about 100 nm. In recent years, wavelengths of light used to fabricate circuits on chips have shortened from 365 nm (i-line) to 248 nm (KrF technology) to 193 nm (ArF technology) and in the future down to 13.5 nm (EUV technology).
Lithography is part of the chip making process whereby a pattern is imaged into the photoresist on the surface of a silicon wafer. It is the critical technology that allows chipmakers to continually shrink IC designs, produce more chips per wafer, improve chip performance and add more on-chip functionality.
A litho-cluster comprises a track system (which coats and develops wafers with photoresist) linked to a lithography system (which images patterns onto the wafers), used for the key stage of chipmaking. The union of these two tools increases productivity and performance. Measurement tools can also be added.
A mask is a flat, transparent quartz plate containing an opaque microscopic pattern: an image of the electronic circuitry for one layer of a chip. The mask is placed in a scanner where intense light passing through it projects the pattern, via a series of reducing lenses, onto part of the wafer. Before exposure, the wafer is coated with photoresist and positioned very accurately- the projected pattern must align with existing features on the chip/wafer. After exposure and developing, the pattern left on the wafer surface is used to selectively process and build up the next layer.
Technology where circuit patterns are written directly onto wafers using either electron beams or light from an array of mirrors.
The co-founder of Intel, Gordon Moore observed in 1965 that the number of transistors that could be placed on a microchip doubles every year. Moore predicted this trend would continue for the foreseeable future. In subsequent years, the pace slowed, but data density doubles approximately every 24 months, giving us the current definition of Moore's Law. Most experts, including Moore himself, expect Moore's Law to hold for some time to come.
The process of accurately measuring structures on a wafer, such as line width or overlay.
Interuniversity Microelectronics Center in Belgium. www.imec.be
A measurement technique that uses the interference pattern created by superposition of (light) waves for accurate position measurement.
A double patterning method using two lithography exposures and hard-mask etches to create smaller chip features. LELE uses fewer processing steps than Spacer double patterning but requires more accurate overlay to align two exposures.
A potential double patterning method using two lithography exposures and two resist layers to create smaller chip features. The method works by 'freezing' the developed resist pattern of the first exposure then adding a second resist layer immediately on top for the second exposure. After developing that, the combined resist pattern is then etched in one go. Since wafers do not leave the litho cluster for the whole process, LFLE is efficient and uses fewer processing steps than both LELE and Spacer double patterning. Various freeze technologies are in development.
A nanometer is one billionth of a meter. It is used to characterize the wavelength of light. A lower nanometer value for the wavelength means semiconductors can be produced that are physically smaller while being faster, more powerful and efficient. Moreover, more transistors can be packed onto the same area.
Numerical aperture or NA
Similar to a camera lens, the numerical aperture determines the resolution: the higher the number, the clearer the view. In the case of lithography, higher resolution allows chip makers to draw more refined features onto silicon wafers. Before the introduction of immersion the perceived barrier for the NA was 1. That barrier was overcome by ASML with the XT:1700Fi: immersion combined with a catadioptric lens design resulted in an NA of 1.2.
Photo resist is light-sensitive material that coats a wafer so images can be etched onto the wafer’s surface. It is resistant to acid and may be a liquid spun onto wafers.
A photoresist consists of a film-forming polymer, a photosensitive material, a solvent and an additive.
When monochromatic light passes through a medium, the ratio of the sine of the angle of incidence to the sine of the angle of refraction is constant and called the refractive index of that medium.
A reticle is a circuit pattern to be projected onto a wafer using UV light. The light reacts with the photoresist and transfers the circuit image on to the wafer. This section of the wafer will eventually become an integrated circuit. The wafer is then moved (stepped) and the process is repeated, until the wafer is covered with many identical patterns, all of which will become ICs.
Chipmaking is all about “shrink” or reducing the size of the chip designs. The shrinking of feature sizes or circuit patterns is central to creating higher performance chips – good news for the end users of the mobile telephones, personal computers and automobiles powered by these ICs. It also results in increased productivity and profitability in factories because there are more chips per wafer.
Coming from sand, silicon is the material from which most semiconductors are made.
To create a wafer from silicon, purified polycrystalline silicon is heated to a molten liquid. A small piece of solid silicon is placed on the molten liquid, and as the seed is pulled from the molten liquid, it cools to form a single crystal ingot. The crystal ingot is ground to a uniform diameter and diamond saw blade cuts the ingot into thin slices of less than 1 mm thickness. This silicon wafer is then chemically polished to give it a reflective luster.
Stepper / scanner
Stepper and scanner lithography systems, such as those made by ASML, are used to print microchip circuit patterns onto silicon wafers. Operating at tremendous speeds, they can print hundreds of chips on every wafer, with features as small as 38 nm, and print up to about 100,000 chip patterns/layers per hour. The first lithography machines were 'wafer steppers' - systems that print whole chip patterns in one go, then 'step' some distance along the wafer to print the next. Today's most advanced machines are 'scanners' or 'step-and-scan' systems. A scanner differs by moving the reticle (pattern mask) and wafer simultaneously in opposite directions while scanning the chip pattern through a slit, line-by-line onto the wafer, before stepping. This allows fast operation with a larger field size (to make larger chips with more functionality), and a more intense, controllable light beam to use the lens better for defining very small features.
A light source, generally a laser, exposes the photoresist or the light-sensitive material that coats a wafer so images can be etched onto the wafer’s surface.
The light source emits a selected wavelength of its irradiation. The projection optics of the exposure tool are designed for this specific wavelength.
Track systems prepare the wafer before and after lithographic systems. A wafer track applies a film of light-sensitive photoresist, and then the coated wafer is delivered by the track to the lithography system for exposure under high intensity light. After the wafer is exposed, the track system is used to develop the image in the photoresist.
The accuracy with which a new pattern is printed on top of an existing pattern on the wafer.
TWINSCAN™ step & scan systems
A unique family of lithography tools designed by ASML, which uses two stages. Two wafers are inside the system at the same time: one wafer is exposed while another wafer is measured. TWINSCAN systems are thus more accurate and deliver more wafers per hour than systems which perform these process steps sequentially.
Expressing the productivity of a system in WPH (wafers per hour).
Polarized light vibrates in only one direction. If you polarize the light, you get a higher quality image with more contrast.
Process factor (k1)
k1 is a process parameter in the Rayleigh equation; its magnitude is proportional to the difficulty of the lithography process. Improvements in the capability of the lithography system, photoresists and mask enhancement technologies, enable lithography at smaller k1 values, which in turn enables the critical dimensions of a chip (minimum feature size) to be reduced.
Spacer is a double patterning technique that uses deposition, anisotropic (directional) etching and trimming to produce smaller features on chips. Basically, it works by depositing a blanket 'spacer layer' over the chip covering all 'hard mask' features. The blanket is selectively etched away leaving two sidewalls along any ridges, then the ridge is removed. What's left are the spacer sidewalls, which have become the new hard mask lines, effectively doubling the number of ridges or lines on the chip. The spacer process is analogous to a blanket of snow -- as it melts, the thicker snow built up against walls and along pavements is left behind. For lithography, the Spacer overlay requirement is less stringent than for other double patterning methods. But in practice, Spacer requires many more processing steps and more lithography exposures for accurate trimming of (NAND) peripheral features.
Co-optimizing the light-source and reticle to improve pattern fidelity and yield.
RET (Resolution/Reticle Enhancement Technology)
A general term describing techniques -- like OPC and off-axis illumination -- for overcoming the diffraction effects of sub-wavelength lithography, enabling circuits to be printed reliably on silicon wafers.
A branch of computational lithography that adds or removes features (serifs) to a reticle pattern to improve printing. The adjustments are calculated and made in simulations to compensate for lens/scanner effects, ensuring that the original, desired IC design pattern can be printed onto the wafer.
Static Random Access Memory, a type of volatile computer memory that is faster, more complex and more reliable than the commonly used DRAM.
A wafer is a thin circular slice of semiconductor material, often silicon, used to make discrete semiconductor devices and integrated circuits (chips). A wafer is typically less than 1 mm thick and its diameter can range typically from about 75 mm to 300 mm. Wafers are made by slicing a cylindrical ingot of single crystal semiconductor material. Using lithography, many chip patterns are printed onto the wafer, and the wafer is diced into individual chips.
The wavelength or color of light radiation used in photolithography systems. The wavelength determines the minimum feature size that can be printed on chips – shorter wavelengths print smaller features. The wavelengths in recent years have shortened from 365 nanometers (older generation = I-line) to 248 nm (KrF technology) to 193 nm (ArF technology). EUV will use a 13.5 nm light source.
The part of a lithography system used to rapidly and accurately position the wafer tables carrying silicon wafers. In a TWINSCAN™ system, wafers are simultaneously positioned under the lens and a measurement system for pre-alignment.
Video Interview: CFO Roger Dassen Q1 Financial Results 2019
Video Interview: CFO Roger Dassen Q1 Financial Results 2019
Annual Report 2018
Annual Report 2018
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