8 days ago - req15185

Design Engineer 2

In a nutshell


San Jose - CA, US


0-2 years





In San Jose, CA, Hermes Microvision seeks Design Engineer 2 to independently develop field-programmable gate array (FPGA) system running at relatively high clock frequency using Verilog/VHDL; develop and debug high-speed serial communication interfaces in complex FPGA designs; perform hardware/software co-development and debug on FPGA SoC devices with ARM processors; work with hardware design engineers to improve system performance and reliability; independently create FPGA designs by performing register-transfer level (RTL) modeling, simulation, synthesis, and timing closure; and work closely with hardware and software engineers to quickly resolve issues.Bachelor’s degree in Electrical Engineering or a closely-related field and 2 years of relevant experience; strong RTL modeling language skills such as Verilog or VHDL; good analog and digital circuit knowledge; strong knowledge in FPGA RTL design, simulation, timing closure, and synthesis; good understanding of UART and SPI communication protocols; solid understanding of EDA tools such as Quartus and ModelSim; ability to operate lab equipment, including oscilloscopes, logic analyzers, and in-system debugging tools such as Signal Tap; experience with SOC embedded system designs and proficient with C/C++; and excellent oral and written communication skills required.Apply online at www.asml.com.EEO/AA (W/M/Vets/Disability) employer.