22 days ago - req32830

Sr. Chip Design Engineer

Research & development

Electrical engineering

In a nutshell

Location

San Jose - CA, US

Team

Research & development

Experience

0-2 years

Degree

PhD

Job Category

Electrical engineering

Travel

10%

Introduction to the job

ASML is a leading supplier of advanced lithography and e-beam wafer inspection and pattern verification systems used for advanced semiconductor devices. The application part of the company has multiple years of e-beam application experience and leadership in semiconductor industry, focused on high resolution and voltage contrast SEM imaging. The application part of ASML will boost ASML’s holistic lithographic portfolio of (i) lithography exposure systems, (ii) computational lithography and (iii) metrology. Between these three cornerstones ASML offers application products for process window enhancement, control and detection. As part of our team, you will have the opportunity to go beyond yourself in developing more advanced techniques and pushing the boundaries of technology.

As an Application-specific integrated circuit (ASIC) design engineer, you will have the chance to join R&D team to work on the advanced analog and mixed signal ASIC for next generation electron detection channel for the leading edge e-beam inspection and metrology systems. Your contributions will help to improve the performance of those products. Our customers will benefit from the performance improvements of products so that they can make more advanced chips with improved yield.

This position may require access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require the Company to proceed with candidates who are immediately eligible to access controlled technology.

Role and responsibilities

  • Identify the design specifications and technical solutions of the signal conditioning chip (ROIC) or chipset based on product roadmap, System Performance Specifications (SPS), and Element Design Specifications (EDS) of the next level sub-system and conduction research and development works in the following areas:
  • Develop new circuit architectures and IPs for next generation signal conditioning ASICs in the detection channel
  • Conduct feasibility study of new ASIC function blocks
  • Work with partners in the design process of the ASICs on the detailed circuit design during the ASIC industrialization phase. Together with the engineering team from the partners, identify design solutions to achieve the specifications of the module / function
  • Review the circuit design of different function blocks i.e., data convertors e.g., analog to digital convertor (ADC), and digital to analog converter (DAC); clock generation circuit e.g., phase lock loop (PLL), delay lock loop (DLL); timing circuit; amplifier e.g., charge transfer amplifier (CTA), transimpedance amplifier (TIA), variable gain amplifier (VGA), programmable gain amplifier (PGA), operational amplifier (OPA), operational transconductance amplifier (OTA), differential amplifier, buffer amplifier, and cable driver, analog switch, voltage reference, current reference, current mirror, and voltage regulator, down to transistor level
  • Conduct pre and post simulation and verification together with engineering team from partners and review the simulation results to ensure that the design can meeting all the specifications
  • Develop EDS and Test Performance Specifications (TPS) and test plan for the Analog and mixed signal ASICs
  • Work closely with the partner to conduct function / performance tests and verification after tape out
  • Support module level and sub-system level integration
  • Generate and / or review related IP documents

Education and experience

Ph.D. with 2+ years of hands-on experiences, or master with 5+ years hands-on experiences, or bachelor with 8+ years hands-on experiences, in electrical engineering.

  • Hands-on experiences of analog and mixed signal IC design, layout, verification, tape out, and test. Familiar with Bipolar, CMOS, and BiCMOS process. Familiar with test equipment such as multi-meter, SMU, signal / function generator, oscilloscope, signal / spectral analyzer, and network analyzer. The successful candidate should be a team player and should have self-motivation, initiative, dedication, and strong communication skills. The candidate should also have the following specific skills or experiences.
  • Minimum qualifications – the hired candidate must possess all of the minimum qualifications to be initially considered for the position including:
  • Familiar with simulation and verification tools from Cadence
  • High performance (high speed, high analog bandwidth and high bit resolution: sample rate goes beyond 1 GS/s, analog bandwidth goes beyond 500MHz, bit resolution goes beyond 10 bits) ADC, and DAC design, layout, tape out and test experiences
  • High performance PLL and DLL design , layout, tape out and test experiences with comprehensive understanding about phase noise and method to reduce phase noise
  • High precision voltage reference (e.g., band gap voltage reference), current source, current mirror, and linear regulator design, layout, tape out and test experiences
  • Analog switch / analog multiplexer (with or without buffer) design, layout, tape out and test experiences with comprehensive understand about charge injection effect in circuit and the method about charge injection effect reduction / cancellation
  • Comprehensive understanding about high performance timing circuit (timing resolution down to at least ps level), timing jitter
  • Additional skills and experiences preferred
  • High performance OPA, OTA, TIA, CTA, LNA and buffer / cable driver design, layout, tape out and test experiences is a plus
  • High performance variable gain amplifier (VGA) design and / or programmable gain amplifier (PGA) layout, tape out and test experiences is a plus
  • DDS IC design, layout, tape out and test experiences is a plus
  • CMOS image sensor design, layout, tape out and test experiences is a plus
  • Passive and active filter design, layout, tape out and test experiences is a plus

Personal Skills

  • Can observe and respond to people and situations and interact with others encountered in the course of work.
  • Can learn and apply new information or skills.
  • Must be able to read and interpret data, information, and documents.
  • Strong customer focus and commitment to customer satisfaction through prioritization, quality, efficiency and professionalism.
  • Ability to complete assignments with attention to detail and high degree of accuracy.
  • Proven ability to perform effectively in a demanding environment with changing workloads.
  • Result driven-demonstrate ownership and accountability.
  • Identifies bottlenecks and drives improvements.
  • Work independently or as part of a team and follow through on assignments with minimal supervision.
  • Demonstrate open, clear, concise and professional communication.
  • Ability to establish and maintain cooperative working relationships with co-workers and customer.
  • Work according to a strict set of procedures within the provided timelines.

Diversity & Inclusion

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.

Other information

  • Must follow the rule / policy of the work location.
  • The position does require working in cleanroom (up to 10% of overall work time) for system level test and debug to verify the concept and / or performance of the designs, or to provide support to sub-system and system level integration.
  • Routinely required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. Occasionally required to move around the campus.
  • Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus.
  • Can work under deadlines.
  • May require travel (domestic and/or international up to : 5% / 10% of overall work time) dependent on business needs.

Requirements within Office

  • Occasionally lift and/or move up to 20 pounds.

Requirements within Lab

  • Capable of operating a variety of test equipment which include but not limited to: oscilloscope, signal generator, signal / spectrum analyzer, vector network analyzer, power supply, source measure unit, multimeter, etc.
  • Ability to do simple PCBA rework and debug.
  • Ability to use tools e.g., screwdriver, wrench, tweezer, pliers, etc. to do simple mechanical assembling and disassembling for test setup.
  • Occasionally lift and/or move up to 50 pounds.
  • For certain tasks, the employer may need to wear personal protective equipment e.g., goggle, face mask, gloves, etc. for a continuous time period of 60 minutes.
  • For certain tasks, the employer may need to work in an enclosed space e.g., shielding enclosure for a continuous time period of 60 minutes.
  • The employee may need to handle bare die / wafer on probe station or under microscope.

Requirements within Factory

  • Must be willing to work in a clean room environment, wearing coveralls, hoods, booties, safety glasses and gloves for entire duration of shift.
  • The employee may occasionally lift and/or move up to 50 pounds.
  • The environment generally is moderate in temperature with moderate to high noise level.
  • Must be willing to work a compressed work week schedule – twelve-hour long shift and rotating from three to four days a week if work on customer site.

EOE AA M/F/Veteran/Disability

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