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Firmware Technical Manager
Research & development
Other technical job categories
In a nutshell
San Diego - CA, US
Research & development
Electrical engineering, Other technical job categories
Introduction to the job
ASML brings together the most creative minds in science, technology and engineering to develop lithography systems that are key to producing faster, cheaper, more energy-efficient semiconductor products. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers – to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. ASML is headquartered in Veldhoven, the Netherlands, and has 18 office locations around the United States. We are currently hiring for senior level FPGA Design engineering positions for our San Diego, CA location.
If you have a passion for technology and innovation you’ll want to check us out. Be a part of ASML. Be a part of progress.
One Company, One Goal, Limitless Innovation. It's our people that make the difference.
This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with applicants who are immediately eligible to access controlled technology.
Role and responsibilities
As an EDEV Firmware Technical Manager you will be in the first-line management layer position.The Technical Manager supervises and manages a team, providing direction and guidance in the Embedded Logic & Firmware competence.The Technical Manager will ensure coordination and execution of operational and tactical-level activities by the team in accordance with the plan and policies in order to achieve goals.The Technical Manager has people management responsibility and also supports manager in building the strategy for the team.
- Supervise a team of FPGA engineers with a typical team size of 5-15 engineers.
- Responsible for the output of the team, the quality of the work, and the well-being of the team.
- Ensures right competencies are in the team and the team follows the right processes.
- Execution responsibility for triple-constraint management (Scope-Time-Cost) and risk management for the team deliverables.
- Setup and maintain the team plan which is connected to the project plan to best support the business roadmap.
- First point of contact for the team; Guards against outside disturbances.Connects the team to relevant designer process and competence leaders.
- Creates an environment in which employees feel engaged and can grow to their full potential through performance management, active coaching and structured people development (technical and non-technical).
Education and experience
- Requires a Bachelor of Science degree in Electrical Engineering or related discipline and a minimum of five (5) years relevant experience.
- Experience in FPGA development, including VHDL for design and System Verilog for verification.
- Excellent written and verbal communication skills.
- Excellent interpersonal and teamwork skills with the ability to influence, motivate, mentor and lead a team.
- Experience taking technical requirements, understanding scope and team required to realize, and leading a team throughplanning and execution in a fast-paced environment.
- Demonstrated creativity in solving complex design problems.
- Ability to use MS Word, Excel, PowerPoint, and electronic e-mail systems.
- Experience in MS Project and SAFe Agile Project Management a plus.
- Experience in team management a plus.
- Collaborate with various areas of the organization to provide technical direction.
- Ensure timely and effective delivery of the solution to the project.
- Uses professional concepts and company objectives to resolve complex product and resourcing issues in creative and effective ways.
- Ensures good team, project and cross-functional communication to ensure coordination between departments/teams/individuals.
- Coach the design team to discover solutions to technical challenges.
- Creates presentations for project/department leadership.
- Leads Embedded Logic & Firmware teams ranging in size from 5 – 20.
- Creates team planning through project lifecycle.
- Provides input for required resources and competence mix for deliverables within agreed timeline.
- Interacts closely with development engineers, suppliers, customer service, manufacturing, safety and QA.
- Other duties & responsibilities assigned.
Diversity & Inclusion
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.
- While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch.
- The employee is occasionally required to move around the campus.
- The employee may occasionally lift and/or move up to 20 pounds.
- May require travel dependent on business needs.
- Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus.
- Can work under deadlines.
We offer competitive salaries and benefits including medical, dental, vision, 401(K), and FSAs.
We are committed to leveraging the diverse backgrounds, perspectives, and experiences of our workforce to create opportunities for our people and the business.
The California base annual salary/hourly range for this role is currently $113,250.00-$188,750.00. Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to, job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Our recruiters can share more information about our bonus program, benefits and equity during the hiring process.
EOE AA M/F/Veteran/Disability
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