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FPGA Engineer - Mid Career
In a nutshell
San Diego - CA, US
Introduction to the job
ASML brings together the most creative minds in science, technology and engineering to develop lithography systems that are key to producing faster, cheaper, more energy-efficient semiconductor products. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers – to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. ASML is headquartered in Veldhoven, the Netherlands, and has 18 office locations around the United States. We are currently hiring for FPGA Design engineering positions at our San Diego, CA location.
If you have a passion for technology and innovation you’ll want to check us out. Be a part of ASML. Be a part of progress.
One Company, One Goal, Limitless Innovation. It's our people that make the difference.
“This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with applicants who are immediately eligible to access controlled technology.”
Role and responsibilities
- Design and develop new protocols to ensure communication between new modules is possible within existing design constraints.
- Define and execute RTL design, Unit Under Test (UUT) level testbenches for simulation, hardware testing and integration support.
- Support verification process and testing by performing requirement traceability, defining and executing Device Under Test (DUT) level test bench setup.
- Create Bus Functional Models (BFMs) and test cases.
- Document and communicate requirements and design details.
- Collaborate in a complex and fast-paced environment with FPGA engineers and multiple engineering groups.
Education and experience
- Bachelor's Degree Preferred with at least 3+ years industry experience in FPGA design and/or verification; completion of at least one full FPGA development cycle.
- If a candidate does not possess a bachelor's degree, we would be looking for at least 6+ years industry experience in FPGA design and/or verification; completion of at least one full FPGA development cycle.
- Proficient in hardware development tools and IDE for Xilinx (Vivado) and/or Altera (Quartus), hardware testing (VIO/ILA/ChipScope, etc).
- Experience with lab hardware debug and usage of IDE debug cores (ILAs, VIOs, SignalTaps).
- Demonstrated proficiency and experience in design using VHDL or verification using System Verilog.
- Experience with System RDL description language.
- Demonstrated ability to translate requirements into design and documentation by means of memory maps, block diagrams (e.g. Visio), tables and text.
- Ability to work independently, as well as to communicate and collaborate with a team.
BSEE or related engineering degree.
- Strong competence in timing simulation/post route simulation and static timing analysis.
Proficient in UVM.
- Experience with automated self-checking test bench verification.
- Demonstrated proficiency and experience in FPGA design and verification methodologies.
Working at the cutting edge of tech, you’ll always have new challenges and new problems to solve – and working together is the only way to do that. You won’t work in a silo. Instead, you’ll be part of a creative, dynamic work environment where you’ll collaborate with supportive colleagues. There is always space for creative and unique points of view. You’ll have the flexibility and trust to choose how best to tackle tasks and solve problems.
To thrive in this job, you’ll need the following skills:
Diversity & Inclusion
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
The California base annual salary/hourly range for this role is currently $98,250.00 -$163,750.00. Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to, job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Our recruiters can share more information about our bonus program, benefits and equity during the hiring process.
EOE AA M/F/Veteran/Disability
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