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FPGA Verification Engineer
Research & development
In a nutshell
Research & development
Introduction to the job
As a Verification Engineer for FPGA designs you are a key technical contributor to a multidisciplinary team of designers who act on (sub-)system level.You take responsibility to set the standard for Verification process in the team and for the verification of FPGA IP blocks (communication link’s, download modules) for new and existing ASML products .
Role and responsibilities
As a Verification Engineer in the Generic Design Blocks (GDB) team you are responsible for the following:
- Act as the EDEV representative in a multidisciplinary design team.
- Interact intensively with colleagues from the software & hardware department.
- Define, document and maintain requirements of various IP’s (firmware GBD’s).
- Define, document, and execute tests to ensure that the firmware satisfy the requirements.
- Perform trade-off studies to determine the preferred implementation scenario for new or changed functions. Get agreement with stakeholders.
- Contribute to GDB roadmap and building-blocks. COTS solutions and using industry standards are highly preferred.
- Make work breakdown and planning for the various firmware products, adjusted with other stakeholders.
- Analyze and solve GDB design issues.
Education and experience
Bachelor- or Master Degree in Electrical Engineering or Computer Science.
- 3+ years of experience as a Verification Engineer with FPGA’s is a must have.
- Extensive experience with System Verilog is a must have
- UVM knowledge is a must have
- Understanding of VHDL / Verilog Designs is a strongly preferred.
- Experience with Assertion Based Verification (SVA especially, PSL) is strongly preferred
- Broad technical knowledge of digital IP’s (Firmware building-blocks) is preferred.
- Experience with Altera / Xilinx Design Flow is preferred.
Working at the cutting edge of tech, you’ll always have new challenges and new problems to solve – and working together is the only way to do that. You won’t work in a silo. Instead, you’ll be part of a creative, dynamic work environment where you’ll collaborate with supportive colleagues. There is always space for creative and unique points of view. You’ll have the flexibility and trust to choose how best to tackle tasks and solve problems.
To thrive in this job, you’ll need the following skills:
- High motivated team player with excellent social, communication andgood coaching skills.
- Ability to give technical direction in a team of designers/verification engineers.
- Able to set the standard and proactively contribute to the Way of Working
- Quality and efficiency focus
- Pragmatic attitude
- Organizes work effectively and logically
- Fluent English in word and in writing
Diversity & Inclusion
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
The sector Development & Engineering (D&E) of ASML is responsible for the specification, design and realization of the products in the ASML portfolio.
Within the sector D&E the department Electronic Development (EDEV) is responsible for the definition, realization, qualification and integration of all electronic functions and modules within these products.
Within EDEV the group Electrical System Architecture (ESA) is responsible for the architecture, design, realization and qualification of electrical functions that are relevant for the system as a whole (i.e. not only for a particular subsystem or component). The GDB team is part of the ESA group and responsible for the development and maintenance of generic FPGA IP blocks (including HW) for all ASML PCBA and FPGA designs.
The Verification Engineer will report to the group leader of the Electrical System Architecture group.
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