Senior FPGA Verification Engineer

In a nutshell


San Diego - CA, US

Published: 30+ days ago Job ID: J-00262473-901

Introduction to the job

ASML brings together the most creative minds in science, technology and engineering to develop lithography systems that are key to producing faster, cheaper, more energy-efficient semiconductor products. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers – to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. ASML is headquartered in Veldhoven, the Netherlands, and has 18 office locations around the United States. We are currently hiring for FPGA Design engineering positions at our San Diego, CA location.

If you have a passion for technology and innovation you’ll want to check us out. Be a part of ASML. Be a part of progress.

One Company, One Goal, Limitless Innovation. It's our people that make the difference.

PLEASE NOTE: This position is a full-time hybrid position which will require the candidate to work in the office 2-3 times a week here in San Diego, CA. The candidate must live or be willing to live, within a commutable distance.

“This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with applicants who are immediately eligible to access controlled technology.”

Role and responsibilities

This job contribute to the specification, design, implementation and validation of FPGAs within highly reliable electronics for ASML's EUV systems. Participate in cross-functional teams and work with multiple engineering groups to design, implement and test new FPGA features .Work with advanced technologies including digital communication, photo-detectors, signal acquisition, and distributed high precision timestamping.

  • Be the owner of lead of the FPGA verification process and testing through qualification of image.
  • Perform requirement traceability via Test Performance Specification (TPS) and capturing results in the Test Acceptance Report (TAR).
  • Support verification process and testing by performing requirement traceability, defining and executing Device Under Test (DUT) level test bench setup.
  • Create Bus Functional Models (BFMs) and test cases, coordinating with Electronics Integration test team.
  • Solve complex system problems, decomposing and providing solutions while guiding and mentoring a team of FPGA verification engineers.
  • Develop new UVM test benches for multiple FPGAs
  • Collaborate in a complex and fast-paced environment with FPGA engineers and multiple engineering groups.

Education and experience

  • 8+ years industry experience in FPGA verification/design.
  • Experience with FPGA verification on Xilinx and/or Altera devices, including SoCs.
  • Experience with Siemens Questasim simulation tool.
  • Experience with System Verilog, Object Oriented Programming and Scripting Languages.
  • Experience with lab hardware debug and usage of IDE debug cores (ILAs, VIOs, SignalTaps).
  • Expert with applicable experience in creating new UVM based test benches.
  • Experience with automated self-checking test bench verification (e.g. developing UVM scoreboards).
  • Demonstrated creative problem solving.
  • Strong ability to collaborate and technically lead while mentoring a cross functional team.
  • BSEE or related engineering degree.

The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.

  • While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch.
  • The employee is occasionally required to move around the campus.
  • The employee may occasionally lift and/or move up to 20 pounds.
  • May require travel dependent on business needs.
  • Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus.
  • Can work under deadlines.

Diversity & Inclusion

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.

Other information

The California base annual salary/hourly range for this role is currently $121,875.00 -$203,125.00. Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to, job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members. Our recruiters can share more information about our bonus program, benefits and equity during the hiring process.

EOE AA M/F/Veteran/Disability

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