VELDHOVEN, the Netherlands, 14 April 2016 –
The introduction of Extreme Ultraviolet (EUV) lithography into volume chip production will be one of the biggest technology transitions that the semiconductor industry has ever undertaken. It will affect not just IC manufacturers and lithography providers but also a wide range of other companies, from resist manufacturers to mask shops and materials suppliers.
The consensus emerging from the 2016 SPIE Advanced Lithography conference – the semiconductor industry’s annual gathering of lithography experts – was that we’re close, but not quite there yet.
(See also: “EUV Lithography – Progress on the Journey to Manufacturing Magic”
and “EUV Becomes an Answer Instead of a Question”
ASML expects the first IC manufacturers to start using EUV for chip production from 2018. With the lead time needed to get systems built, installed in fabs and qualified for production, this means 2016 is the year when the in-principle decision to insert EUV in 2018 will have to be made.
Not surprisingly, investors, partners, suppliers and other stakeholders have a keen interest to understand how this decision is shaping up. They should watch the key economic metrics of EUV, the productivity and availability of the lithography system – but in the knowledge that there are a number of other considerations, some of them customer or application-specific, that will play a role as well.
There is no doubt that EUV scanners can print chip features for the next technology nodes
First it should be noted that the lithographic performance of EUV scanners is excellent, and has been for several years. There is no doubt that EUV scanners can print chip features for the next technology nodes. Resolution, pattern fidelity, overlay and focus accuracy all meet the requirements.
For example, the NXE:3350B EUV system achieves overlay below 1.5 nanometers, and focus uniformity below 10 nanometers. (More details here.
Further underscoring that point, functioning test chips have already been manufactured with EUV
Cost, benefits and risk will drive the decision to use EUV in volume production
The decision when to use EUV in volume manufacturing goes beyond lithographic performance; it is a business decision that will be framed in terms of cost, benefits and risk.
A number of factors influence the cost-benefit assessment: the total cost of ownership of the two alternatives (EUV and immersion multiple patterning), but also factors such as the expected time to market.
Since a leading-edge multiple patterning process requires up to twice as many total lithography exposures as an EUV-based process, it takes longer to develop and has smaller margins of error. An EUV-based process thus has advantages in terms of expected yield and time to market.
Next to the price of the tool and the operating expenses of running an EUV system, total cost of ownership is driven by the equipment efficiency – the number of wafers that the EUV system can process in a certain amount of time (usually measured per hour or per day) and the amount of time that the system is available to process wafers (usually expressed in percentage per day). A chip fab operates 24 hours a day and 7 days a week, so customers are looking for both high productivity and high availability to use their manufacturing assets to the fullest extent.
Based on our modelling, confirmed through regular interaction with customers, we believe that a productivity of around 1,500 wafers per day makes EUV more cost-effective than multiple patterning. When taking into account the additional benefits of EUV, such as better yield and faster time to market, the cost cross-over point may even be substantially lower.
ASML’s 2016 productivity target is to achieve the 1,500 wafer-per-day milestone. The 2016 target for availability is 80 percent, but it is clear that availability needs to continue to improve further, towards the levels that are achieved by immersion systems today (above 95 percent).
On both fronts, ASML is on track.
Multiple EUV systems, both at ASML and at customer sites, have demonstrated the capability to process more than 1,000 wafers per day. ASML’s latest EUV system, the NXE:3350B, has shown a peak productivity of 1,368 wafers in a 24-hour period.
Customers have also tested the system over longer periods of time, and in a recent two-week run, a system exposed an average of just under 800 wafers per day with an availability of more than 85 percent.
The large majority of systems at customer sites have demonstrated a 4-week average availability of at least 70 percent.
In a recent interview, ASML Chief Executive Peter Wennink acknowledged that due to past delays, chip makers still harbored some doubts, but noted that the recent progress with the EUV source had built confidence.
“EUV turned out to be more complex than we thought seven or eight years ago. We didn’t know what we didn’t know. We know a lot more today,” Wennink said.
“There’s still a lot of work to be done, but we’re confident that we will meet the 2016 targets, which are a very important milestone for the 2018 introduction,” Wennink said.
This webpage contains statements relating to certain projections and business trends that are forward-looking, including statements with respect to our outlook, expected industry trends, productivity of our tools and systems performance, and EUV system performance, targets (including availability, productivity and shipments) and roadmaps. You can generally identify these statements by the use of words like "may", "will", "could", "should", "project", "believe", "anticipate", "expect", "plan", "estimate", "forecast", "potential", "intend", "continue" and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about the business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors (the principal product of our customer base), including the impact of general economic conditions on consumer confidence and demand for our customers' products, competitive products and pricing, the impact of manufacturing efficiencies and capacity constraints, performance of our systems, the continuing success of technology advances and the related pace of new product development and customer acceptance of new products, the number and timing of EUV systems expected to be shipped and recognized in revenue, delays in EUV systems production and development, our ability to enforce patents and protect intellectual property rights, the risk of intellectual property litigation, availability of raw materials and critical manufacturing equipment, trade environment and other risks indicated in the risk factors included in ASML's Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. These forward-looking statements are made only as of the date that this webpage was posted. We do not undertake to update or revise the forward-looking statements, whether as a result of new information, future events or otherwise.