Santa Clara, California, June 11, 2003
ASML MaskTools today announced that Nanya Technology Corporation of Taiwan has licensed its proprietary software and intellectual property for deployment in Nanya's advanced semiconductor production facilities. The capabilities provided by ASML MaskTools will enable Nanya to improve imaging performance in its next-generation process technologies.
Nanya, one of the top manufacturers of DRAM chips in the world, will use MaskRigger software to implement Scattering Bar technology on its photomasks to significantly improve the image quality of the design patterns being transferred from mask to wafer. Specific benefits include improved depth of focus (DOF), greater process latitude, better critical dimension (CD) uniformity and higher manufacturing yields.
This agreement demonstrates the increasing importance of ASML’s software and intellectual property in high-volume chip manufacturing as it follows on the heels of a similar licensing agreement between ASML and another leading DRAM manufacturer.
“ASML MaskTools is pleased to add Nanya to its growing list of customers for our patented scattering bar technology. This has proven to be widely applicable for high volume DRAM manufacturing,” said Dinesh Bettadapur, president and CEO, ASML MaskTools. “Nanya will benefit from the enhanced imaging performance offered by our complete solutions package which includes full-chip implementation software, manufacturing IP and applications support.”
About ASML MaskTools
ASML MaskTools, based in Santa Clara, California, offers leading edge optical extension technologies and products for the semiconductor industry. Core products include MaskWeaver for full-chip OPC/CPL/DDL mask optimization, MaskRigger for full-chip rule-based OPC/PSM implementation, and LithoCruiser for lithography process analysis and optimization. As optical lithography continues to be used for volume IC manufacturing below the wavelength of the exposure light source, these technologies and products enhance photolithography process latitude, thereby improving integrated circuit yields in manufacturing.
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