An innovation leader in the semiconductor industry, ASML’s lithography solutions have been making giant leaps on this tiny scale since 1984. In our technology, hardware meets software to provide a holistic approach to mass producing patterns on silicon.

How lithography works

A lithography system is essentially a projection system. Light is projected through a blueprint of the pattern that will be printed (known as a ‘mask’ or ‘reticle’). The blueprint is four times larger than the intended pattern on the chip. With the pattern encoded in the light, the system’s optics shrink and focus the pattern onto a photosensitive silicon wafer. After the pattern is printed, the system moves the wafer slightly and makes another copy on the wafer.

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This process is repeated until the wafer is covered in patterns, completing one layer of the wafer’s chips. To make an entire microchip, this process will be repeated 100 times or more, laying patterns on top of patterns. The size of the features to be printed varies depending on the layer, which means that different types of lithography systems are used for different layers – from our latest-generation EUV (extreme ultraviolet) systems for the smallest features to older DUV (deep ultraviolet) systems for the largest.

EUV lithography

ASML is the world’s only manufacturer of lithography machines that use extreme ultraviolet light. EUV lithography uses light with a wavelength of just 13.5 nanometers (nearly x-ray level), a reduction of almost 14 times that of the other enabling lithography solution in advanced chipmaking, DUV (deep ultraviolet) lithography, which uses 193-nanometer light.

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Our EUV platform extends our customers’ Logic and DRAM roadmaps by delivering resolution improvements, state-of-the-art overlay performance and year-on-year cost reductions. Our EUV product roadmap will drive affordable scaling to 2030 and beyond.

To harness the power of extreme ultraviolet light and bring EUV lithography to the market, ASML had to tackle some of its biggest technical challenges over more than 20 years of sustained R&D. These challenges included fundamental paradigm shifts in lithography system architecture, such as imaging in high vacuum instead of air, working with ultra-flat multi-layer mirrors instead of lenses, and generating the required light by vaporizing droplets of tin with a high-power laser.


We are developing a next-generation EUV platform with a higher numerical aperture of 0.55 (“High-NA”). This platform has a novel optics design and significantly faster stages. It will enable geometric chip scaling beyond the next decade, offering a resolution and overlay capability that is 70% better than our current EUV platform. The High-NA platform has been designed to enable multiple future nodes, starting at the 3-nanometer Logic node and followed by memory nodes at similar density.

DUV lithography

Our DUV (deep ultraviolet) platform is the industry ‘workhorse’, offering immersion and dry lithography solutions that help manufacture a broad range of semiconductor nodes and technologies. Our immersion and dry systems lead the industry in productivity, imaging and overlay performance for high-volume manufacturing of the most advanced logic and memory chips. Our immersion systems can deliver both single-pass and multi-pass lithography and have been designed to be used in combination with EUV lithography to print the different layers of a chip.

Metrology & inspection

Our metrology solutions can quickly measure imaging performance on silicon wafers and feeds that data back into the lithography system in real-time, helping to keep lithography performance stable in high-volume chip manufacturing. Our inspection solutions help to locate and analyze individual chip defects amid billions of printed patterns.


If our hardware innovations are Batman, then software is its Robin. Even though you might know of ASML as a hardware company, we actually have one of the world’s largest and most pioneering software communities. It would be impossible for our lithography systems to manufacture chips at such increasingly small dimensions without the software we develop. As a result, our lithography systems are now a hybrid of high-tech hardware and advanced software. Our development teams work across a range of coding practices, providing innovative solutions to the intricate problems that affect the chip-making systems at the heart of the electronics industry.

What’s next?

In 1965, Gordon Moore, one of Intel’s co-founders, predicted that the number of transistors in a chip would double every two years, exponentially increasing the computing power and decreasing the cost. Moore’s prediction has proved to be true – or, as some argue, a self-fulfilling prophecy. The industry recently celebrated 50 years of ‘Moore’s Law’, and today’s chips contain tens of billions of transistors.

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Extending Moore’s Law is becoming increasingly difficult and costly. But we aren’t as close to the fundamental limits of physics as some would have us believe. Next-generation chip designs will include more exotic materials, new packaging technologies and more complex 3D designs. These new designs will help to generate consumer products that right now we can’t even conceive of. They will also enable the next big waves of innovation on the horizon, such as automated transportation, advanced AI and fast connectivity with 5G.

What will always be needed is a way to mass produce these designs at the right cost. That’s where the full scope of ASML’s product portfolio will continue to play a big role, working holistically to ensure affordable transistor shrink. We continue to push our entire system portfolio to new productivity levels and imaging performance. Our EUV and High-NA lithography will enable tomorrow’s most advanced chips. In our computational lithography solutions, we’re bringing machine learning and big data to the forefront in predicting both lithography and metrology processes with 100% accuracy. Finally, we’re developing an entirely new class of e-beam inspection systems to help chipmakers control defectivity in manufacturing next-generation chip nodes.