4-minute read - by Sue Todd, May 23, 2021
Imagine you are asked to build the world’s tallest skyscraper. On uneven land. With no room for error and every story aligning perfectly with one another. Oh, and you have to do this all on the nanometer scale. Sound impossible? ASML’s engineers face this challenge every day with 3D NAND chips – but they are making them a reality through our expertise in an area known as scanner metrology.
3D NAND is a type of microchip with non-volatile memory, also known as flash memory, which supports high-performance electronics and innovations such as automated vehicles, advanced AI and 5G connectivity. It is made of stacks of memory cells placed on top of each other in order to create a multi-story, 3D-chip structure.
This relatively new type of chip design addresses the challenge of the limited amount of bits that can fit on a two-dimensional cell. A 3D NAND chip is able to hold more bits, run more efficiently and use less energy than their 2D counterparts. But it is more difficult to make.
A 2D microchip goes through hundreds – sometimes thousands – of different processes to make just one layer of a working device. This year, 3D NAND chips that have 176 layers were released, so it’s no surprise that fabricating these chips requires an even more intricate production process.
Precision and alignment
The crux of this challenging undertaking is to ensure the stack of layers is constructed uniformly and aligned with sub-nanometer precision to then be connected using tiny vertical channels. Alignment is an integral part of printing chip patterns on wafers, and for 3D NAND the pressure is ramped up.
“Instead of making bungalows, we’re now making multi-story skyscrapers. As you can imagine, this is a highly complex undertaking,” says Steven Steen, director of 3D product management at ASML.
As the number of layers increase, the challenge of assessing the accuracy and quality of production becomes even more important and more complex. How can you look inside these opaque, nanometer-sized 3D structures to gather information on channel alignment and identify fabrication issues? And how do you manage the huge amount of data generated?
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The incredible volumes of data that need to be processed resemble the never-ending patterns of a fractal – the naturally occurring repetition of patterns on smaller and smaller scales in everything from the fronds of a fern to the spiral arms of our galaxy.
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“Basically, you take everything you’ve measured in alignment and overlay and then back-calculate this to correct for any inaccuracies,” Steen explains.
“We’re working on thicker stacks on the wafer, comprising different materials, with different expansion coefficients. That can lead to deformation of the wafer on the x, y and z plane.”
For example, the z plane often curls up – a little like wet paper, but on a nanometer scale. This is an issue when you’re stacking multiple layers on top of one another – especially as each new layer requires at least one pass through the lithography system – because exactly aligned overlay is critical to make any integrated circuit work.
In lithography, engineers also have to correct for some of the challenges of processes further down the line: for instance in the drilling of the connecting vertical channels, alignment issues can result from lateral effects, leading to tilt and bowing and non-vertical channels.
