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Find your passion at ASML Silicon Valley
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Read about Mingjing Zhao, a senior software quality assurance manager at ASML in Silicon Valley, and other women as they pursue their dreams in computer science and software engineering at ASML.
Jinping Song, Head of HMI and Brion DevOps Team
Abhishek Vikram, Director of Product Management "The Silicon Valley site works together with colleagues around the world to deliver a holistic solution to customers by providing our unique competency."
Sheila Kang, Senior Software Engineer
Mohamed Ali, Software Platform Engineering ManagerDiscover what ASML has to offer in San Jose.
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Create job alertThe complexity of the physics and sheer scale of the optimization problems faced at ASML Silicon Valley present challenges of their own. Today’s chips have billions of transistors, built up layer by layer with extreme precision, requiring the imaging of tens of billions of patterns that must be simulated and optimized within 24 hours – it’s an enormous, time-sensitive task. At ASML Silicon Valley, we develop innovative ways to speed up the model calculations. We harness the power of tens of thousands of computing cores to quickly process full chip blueprints – all without sacrificing accuracy. This is an iterative, computationally intensive process that requires the efficient and accurate utilization of a large-scale, distributed high-performance computing architecture.
Today’s mainstream optical inspection technologies are reaching their resolution limits. With its high image resolution, e-beam metrology technology is becoming necessary to achieve accurate measurements and address shrinking margins of error. In Silicon Valley, we’re creating a new class of applications to ensure accurate wafer patterning performance and identify yield-related defects faster with higher accuracy across more wafers at the most advanced nodes.
E-beam technology uses a focused stream of electrons to measure chip geometries that are much smaller than those resolved by even the most advanced optical technology. ASML Silicon Valley brings additional metrology capability such as high-resolution imaging and voltage contrast that checks the integrity of the electrical properties of interconnect layers.
We use high-resolution e-beam images from e-beam metrology systems to improve our computational lithography models. These improved models are then used to enhance scanner control, leading to improved yield.
